1. Technical Field of the Invention
The present invention generally relates to telecommunications. More particularly, and not by way of limitation, the present invention is directed to bandwidth grooming functionality in an access network element.
2. Description of Related Art
The remote access market is undergoing a major metamorphosis. Three factors serve as catalysts for change. The first is the growing number of users, for example, small office/home office (SOHO) users, demanding high performance Internet and remote access for multimedia. Liberalized governmental activity with respect to telecommunications is another factor, which is fostering broader competition through deregulation in local area markets everywhere. The third and final factor is congestion in the Public Switched Telephone Network (PSTN), originally designated and developed for voice-only traffic.
There have been several important advances in telecommunications technology that enable high rates of throughput in carrier networks' backbone connections. For example, by implementing Asynchronous Transfer Mode (ATM) networking technology over a Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) physical layer, carrier networks can achieve data rates of up to several hundred megabits per second (Mbps). However, efforts to meet the bandwidth demand for remote access have been beset by the limitations of the existing twisted-pair copper cable infrastructure (i.e., access network) provided between a carrier's central office (CO) and a subscriber's remote site, typically referred to as the local loop. In the telecommunications art, these limitations are sometimes collectively described as the “last mile” problem.
Current access network solutions that attempt to avoid the bottleneck created by the last-mile problem involve the use of fiber optic technology in the local loop also. As with the high-speed carrier networks, the fiber-based local loop infrastructures are typically architected using SONET as the physical layer technology. With recent developments in optical components and related opto-electronics, in addition to improvements in network design, broadband access is now becoming commonplace.
Moreover, coupled with the phenomenal growth in the popularity of the Internet, there has been a tremendous interest in using packet-switched network (PSN) infrastructures (e.g., those based on Internet Protocol (IP) addressing) as a replacement for the existing circuit-switched network (CSN) infrastructures used in today's telecommunications networks. From the network operators' perspective, the inherent traffic aggregation in packet-switched infrastructures allows for a reduction in the cost of transmission and the infrastructure cost per end-user. Ultimately, such cost reductions enable the network operators to pass on the concomitant cost savings to the end-users.
As can be appreciated by one skilled in the art, concomitant with the aforesaid developments, access networks are being required to handle ever greater amounts of traffic. Whereas an access network node may be provided with an increased number of links in order to handle raw transport bandwidth needs, various internal architectural constraints necessarily follow, especially with respect to the switching functionality of the node.
It is well-known that the switching functionality of telecommunications network nodes, including access terminals, is vital to the performance of the deployed infrastructure. Essentially, the demand for greater number of links to be provisioned for an access terminal translates into a need for a more robust and sophisticated system for storing and processing bandwidth at the switching “fabric” of the terminal.
Conventionally, a time slot interchanger (TSI) mechanism is employed for effectuating a terminal's switching functionality. One existing solution for storing and processing more bandwidth at the TSI is to increase the size of the memory and associated hardware supporting the TSI. Whereas this solution and related variants can be effective in some implementations, they are nonetheless beset with certain shortcomings and deficiencies. First, the additional memory adds hardware cost to the system and introduces a greater probability of error. Moreover, implementing additional memory typically requires a more sophisticated busing structure which adds further complexity to the system. Further, the increased amount of hardware uses valuable “real estate” in today's already crowded access products where stringent form factor requirements exist. Additionally, the current hardware solutions make upgrading of extant access products difficult.